This invention is especially useful in testing flip-chip devices. As shown in the illustration of a single flip-chip device 102 in FIG. 1A, such flip-chip devices typically have solder bumps 104 on a face of the flip-chip that are the electrical connections to the flip-chip 102. The flip-chip 102 is encapsulated in a larger package 112; and solder bumps 104 are connected via connectors schematically represented by lines 108 through a packaging substrate 106 to larger package solder bumps 110 (e.g. in a Ball Grid Array (BGA) configuration). The package solder bumps 110 are used to connect the entire package to a printed circuit board (PCB) or other electronic device. The solder bumps 104 of the flip-chip 102 are critical to the operation of the flip-chip device, as they provide the electrical connections into and out of the flip-chip.
Integrated chip devices may include Boundary Scan Testing (BST) architecture in accordance with IEEE Standard 1149.1 developed by the Joint Test Action Group (JTAG). BST architecture offers the capability to efficiently test components on printed circuit boards with tight lead spacing. Pin connections on a device can be tested and functional data captured using the BST architecture with or without physical test probes. BST architecture adds four or five test pins to the device and embeds test circuitry at chip level to provide access to chip assemblies for testing, debugging and in-system device programming. As illustrated in FIG. 1B, boundary scan cells 126 are connected to solder bumps 124 and the core logic 122 of the device via connectors 128 and 132, respectively. Additionally, boundary scan cells 126 are connected in series to each other via connectors (e.g., 130 and 138). Boundary scan cells can force signals onto and capture signals from device solder bumps 124 or core logic 122. Test data is serially shifted into the boundary scan cells 126 associated with each device solder bump through a Test Data Input (TDI) pin 134 on the device. Captured test data is serially shifted out of boundary scan cells 126 through a Test Data Output (TDO) pin 136. The captured test data is then compared with expected results to determine errors in the device. Although solder bumps 124 are shown on the sides of the integrated circuit device 120 for ease of illustration, typically the solder bumps will be on top of the integrated circuit device 120 (i.e. on the surface of the device coming out of the plane of the page in FIG. 1B; e.g., see the side view shown in FIG. 1A).
Before they are incorporated into a larger electronic device, semiconductor electronic devices are usually tested using Automatic Testing Equipment (ATE) systems. These systems include a tester and a prober with a test head and probe card assembly acting as the interface between the tester and device under test (DUT). The P-8 or P-12 systems manufactured by Tokyo Electron Limited (TEL) of Tokyo, Japan, are examples of prober systems. In the illustrative system shown in FIG. 2, a tester 202 includes a tester computer 206 and a tester controller 208 with various electronics and drivers to provide power and test signals to DUTs. The tester controller 208 includes electronics for controlling and operating the tester and interface card. An independent voltage source (not shown) may also be included in the tester controller electronics. A test head 212, a probe card 214 and probe card contacts 216 are connected by appropriate cabling 210 to the tester controller 208. The tester computer 206 includes at least a central processing unit (CPU), a user or system operator interface, a system memory for storing data and software programs and buses for connecting the various parts of the system. The memory can store programs for signaling the tester controller 208 to apply various electrical signals for testing devices. Test programs typically include test vectors that have a test data stream and a corresponding expected device response data stream for the DUT.
A prober 204 includes a test head/probe card holder (not shown) and a prober controller 220 for controlling the movement of a wafer chuck 226 in which a wafer 228 is mounted. The prober 204 has a prober computer 218 connected to the prober controller 220. In combination, the prober computer 218 and the prober controller 220 direct the movement of a wafer table 222, as described below. The prober computer 218 includes at least a central processing unit (CPU), a user or system operator interface and a system memory for storing data and software programs. The memory stores programs for signaling the prober controller 220 to apply various electrical signals for operating the wafer table 222 to move device wafers into contact with the probe card contacts 216. Both the prober computer 218 and the tester computer 206 may be programmed separately or in conjunction with each other with software program modules designed to operate the prober and tester systems.
The wafer table 222 includes a mechanism 224 for moving the wafer chuck 226 in three dimensions (shown in FIG. 2 by the heavy two-way arrows at 230) to bring a wafer 228 into precise contact with the probe card contacts 216 of the tester 202. The wafer 228 usually includes a two-dimensional array of a plurality of integrated circuit devices (or chips) on its surface. Illustratively, these devices are flip-chip devices such as flip-chip 102 shown in FIG. 1 that have solder bumps on one side of the device. The probe controller 220 controls the movement of the wafer chuck 226, and thereby the location and movement of one or more flip-chips being tested. Through the prober computer 218, the probe controller 220 provides position information to the tester computer 206 via connection 232 so that the test computer can match test signals and response data to the one or more specific devices being tested. Connection 232 is typically a RS232, GPIB, USB, serial port or parallel port connection.
Communications between the tester 202 and prober 204 are carried by connection 232 and typically take the following form. The tester computer 206 includes a test program that sends a signal to the prober computer 218 to move a specific die under the probe card contacts 216 for testing. Following practice in the industry, we refer hereafter to this die as the device under test (DUT). The prober computer 218 includes program modules for receiving the signals from the tester computer 206 and translating the signals into device coordinates on the wafer. The prober controller 220 then moves the DUT horizontally under the probe card contacts 216, and then moves the wafer chuck 226 vertically so that the DUT comes into contact with the probe card contacts 216. Contact here may be actual physical contact, or it may be that a pre-set vertical distance is specified in the prober computer program such that once the wafer chuck is raised that distance the prober controller considers itself to be in contact for the next steps. Further, an overdrive distance may be programmed in the prober computer 218 or provided to the prober computer by the tester computer 206 in order to raise the wafer chuck 226 a further distance beyond initial contact. The overdrive distance compresses some or all of the solder bumps on the DUT and some or all of the probe card contacts, which typically have a spring element. The prober computer 218 then signals the tester computer 206 that the DUT is in contact and may be tested. The test program in the tester computer 206 then signals the tester controller 208 to drive test signals and power through the test head 212 and probe card contacts 216 into the DUT. The DUT's response is received back through the probe card contacts 216, is captured by the tester controller 208, and compared by the tester computer 206 to expected results to determine errors in the DUT. Alternatively, for devices that have BST architecture, in one testing mode test signals are provided through the TDI pin to the boundary scan cells; and the test signals are then driven out of the DUT to the probe card contacts. In a second testing mode, test signals are applied to the DUT through the probe card contacts and are received by the boundary scan cells. These signals may then be read out of the DUT through the TDO pin. With or without BST architecture, an error is found when the actual response signals from the DUT do not match the expected signals. Once the test is completed, the tester computer 206 signals the prober computer 218 that the test is completed and that another device should be moved into contact with the probe card contacts 216 for testing.
Several different types of probe card contacts are known in the art, such as the Vertical Spring Card (VSC), the COBRA-type vertical probe, cantilever needle and the form factor spring. The type primarily referred to throughout this application is a flat tipped vertical probe card contact, such as in VSC or COBRA-type vertical probe systems. A standard flat tipped vertical probe card contact is cylindrical with a flat bottom face used to contact the test site. Such flat tipped contacts apply a downward normal force to the top of a solder bump when the wafer is brought upward into contact with the vertical probe card contacts by the wafer prober.
Regardless of the type of probe contact employed, electrical contact between the contacts on the probe card and the contacts on the DUT is essential for a valid test. In other words, if signals cannot effectively get from the tester into the DUT circuit and vice versa, there is no way to test or even use the DUT. A significant problem in this regard is the formation or collection of resistive and capacitive substances, such as oxides, on the surface of the electrical contacts of the DUT. For example, in flip-chip devices, an oxide formed on the solder bump introduces capacitance and resistance between the DUT's solder bump and the probe card contact. Such oxides are usually formed due to the exposure of the solder bumps to air. If the oxide raises the capacitance and resistivity high enough, no current will pass through the oxide and the DUT will fail the test. Alternatively, the capacitance and resistivity may reduce the speed and/or amplitude of the electrical signals being passed to the DUT to such an extent that a voltage high signal (e.g. a digital “1”) may appear as a voltage low signal (e.g. a digital “0”) on the device side of the oxide. Further, at-speed testing of a device's functions requires testing the device at or near normal operating speeds (i.e. typically up to about 200 MHz). An added capacitance and resistance may slow the transmission of signals to and from the device such that the device will not function at a 200 MHz speed. An oxide may cause false negatives in the testing of DUTs, and it may require that the tests be repeated. Testing devices is a time consuming and expensive activity, and requiring multiple tests only increases the time and expense. Additionally, the probe card contacts have a limited life, and multiple tests on each wafer will degrade the probe contacts that much faster.
Several techniques have been employed to address this problem. Such efforts have included repetitive touchdowns, keeping the wafer stored in an inert atmosphere cleaning the wafer probes and solder bumps. These add to the testing time and cost, and may not solve the problem in any case for all solder bumps on a given DUT, especially as solder bump sizes and densities continue to decrease along with DUT voltage and current tolerances. Additionally, various probe card contact configurations have been tried, such as the cantilever needle and form factor spring contact assemblies, to employ mechanical means for overcoming the resistance on contacts. However, such mechanical means have various significant drawbacks, as well. For instance, such mechanical means are often restricted in the depth of the array of solder bumps that can be probed. Additionally, these mechanical means tend to leave an indentation in the surface of a solder bump, which raises reliability concerns because of trapping contaminants in the indentation or creating voids in the joint that this solder bump forms with the package substrate.
Thus, none of the aforementioned techniques consistently provide good electrical contact and signal integrity between the DUT and automatic test equipment for all solder bump surfaces; and a need remains for an improved means for making electrical contact and ensuring signal integrity between probe card contacts and solder bumps.